In the field of non-volatile memories, flash memory scaling beyond a 45 nm node has become a real issue. Technologies to face this challenge are ferroelectric, magnetic and phase change memories, the latter one being promising for the replacement of flash and showing characteristic that may allow replacement of other types of memories such as DRAM. Phase change memories are a possible solution for the unified memory being an important step in the electronics art. OTP (“on time programmable”) and MTP (“multiple times programmable”) memories open a field that may present a great opportunity for phase change memories as well.
Phase change memories are based on a reversible memory switching using, for instance, chalcogenide materials. Thus, phase change materials may be used to store information. The operational principle of these materials is a change of phase. In a crystalline phase, the material structure is (and thus properties are) different from the properties in the amorphous phase.
In silicon-based memories, the programming of a phase change material is based on the difference between the resistivity of the material in its amorphous and crystalline phase. An electrical current may be used to sense such a difference. By tuning this electrical current, writing may be also possible.
To switch between these phases, an increase in temperature is required. Very high temperatures with rapid cooling down will result in an amorphous phase. A smaller increase in temperature or slower cooling down may lead to a crystalline phase.
In a silicon-based memory, the principle is that the increase in temperature may be obtained by applying an electrical pulse to the memory cell. A high current density may lead to a local temperature increase. Depending on the shape of the pulse, the temperature profile may be different, resulting in one phase or another.
FIG. 2 shows a diagram 200 having an abscissa 201 along which the time is plotted. Along an ordinate 202, a temperature is plotted.
FIG. 2 shows temperature profiles obtained by applying electric pulses to conventional chalcogenide based phase transition material memories for switching the memory between the two phases. A first pulse 203 may be applied as a RESET pulse for amorphizing such a chalcogenide material. A second pulse 204 may be denoted as a SET pulse and may be used for crystallizing a chalcogenide-based memory. A time t1 is indicative of a time interval during which the first pulse 203 is changed between a temperature Tm and a temperature Tx. A second time interval t2 denotes a time interval which the second pulse 204 needs to be changed from Tx to an essentially constant asymptotic value.
The SET and RESET temperature profiles shown in FIG. 2 can be applied to a conventional phase change material memory 300 as shown in FIG. 3.
In the phase change material memory 300 shown in FIG. 3, a resistor 301 having a modifiable resistivity (realized as a phase change material) is arranged between a supply voltage reference Vdd and a drain voltage VD of a switch transistor 302. The source of the switch transistor 302 is connected to the reference potential Vs=0. Furthermore, a gate voltage VG may be applied to the gate of the switch transistor 302 to selectively enable or disable access to the switch transistor 302.
The increment in temperature in a phase change cell 300 is proportional to the power applied to the memory cell 300. The transistor 302 driving the memory element 301 is designed to stand a power level proportional to the one applied to the phase change element 301 (as the transistor 302 is in series with the phase change element 301). This means that when the phase change element 301 has a higher power necessity, the transistor 302 should stand more power.
As depicted in FIG. 4, the amorphisation pulse 203 is an electric pulse that needs to dissipate more power than the crystallisation pulse 204.
In FIG. 4, a diagram 400 is shown having an abscissa 401 along which a pulse width in nanoseconds is plotted. Along an ordinate 402 of the diagram 400, a power in Watt is plotted. FIG. 4 shows a minimum amorphisation power 203 versus crystallisation power 204 in a line phase change cell. It can be seen that the crystallisation power 204 is lower than the amorphisation power 204.
Hence, the transistor 302 will need more drive power when programming the amorphous state. On the other hand, the transistor 302 size depends on the power it needs to withstand. In conclusion, the transistor 302 dimensions are given by the power requirements of the amorphisation pulse 203.
FIG. 5 shows a diagram 500 having an abscissa 501 along which a pulse width in nanoseconds is plotted and having an ordinate 502 along which a current in arbitrary units is plotted. A first curve 503 shows a RESET current and a second curve 504 shows a SET current, for an exemplary cell.
Therefore, FIG. 5 shows programming currents for SET (crystallization) 504 and RESET (amorphisation) 503 for different pulse widths in a phase change line of an exemplary cell. The SET state can be achieved with currents lower than a threshold value. In the case of RESET pulses, currents over a threshold value are required.
FIG. 6 shows a diagram 600 having an abscissa 601 along which a channel width is plotted in nm and having an ordinate 602 along which a drain current is plotted in mA. Drain current saturation is indicated by reference numeral 603.
Thus, FIG. 6 shows NMOS Ids currents used in the design of a phase change memory array. In other words, FIG. 6 shows data for a 200 nm long NMOS transistor used in a phase change memory. According to FIG. 5, a 100 ns pulse of less than a threshold value can SET a cell. To RESET a cell with 100 ns, a certain current is required. To get a SET current, a 200 nm length by 400 nm width transistor can be used. The minimum transistor that can provide the RESET current is a 200 nm length by 800 nm width. This means that RESET currents need a transistor twice as big as a transistor used to drive the SET current.
Consequently, the space used in a phase change memory is mainly determined by RESET currents and the required transistors to handle them. Conventionally operated phase change memory cells are therefore large due to the necessity of large transistors and are prone to failure since large programming currents are required.
EP 1,233,418 A1 discloses an ultra-high-density data-storage media employing indium chalcogenide, gallium chalcogenide, and indium-gallium chalcogenide films to form bit-storage regions that act as photoconductive, photovoltaic, or photoluminescent semiconductor devices that produce electrical signals when exposed to electromagnetic radiation, or to form bit-storage regions that act as cathodoconductive, cathodovoltaic, or cathodoluminescent semiconductor devices that produce electrical signals when exposed to electron beams. Two values of a bit are represented by two solid phases of the data-storage medium, a crystalline phase and an amorphous phase, with transition between the two phases effected by heating the bit storage region.
However, the high power demand of the electric heating procedure according to EP 1,233,418 A1 may be problematic.